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| 1 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms key timing parameters speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns dram module mt8ld864a x, mt16ld1664a x, mt32ld3264a x for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/datasheet.html pin assignment (front view) features ? eight-cas# ecc pinout in a 168-pin, dual in-line memory module (dimm) 64mb (8 meg x 64), 128mb (16 meg x 64), and 256mb (32 meg x 64) nonbuffered high-performance cmos silicon-gate process single +3.3v 0.3v power supply all inputs, outputs and clocks are lvttl- compatible 4,096-cycle cas#-before-ras# (cbr) refresh distributed across 64ms extended data-out (edo) page mode access cycle serial presence-detect (spd) options marking package 168-pin dimm (gold) g timing 50ns access -5 60ns access -6 access cycle edo page mode x pin symbol pin symbol pin symbol pin symbol 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 oe2# 86 dq32 128 r f u 3 dq1 45 ras2# 87 dq33 129 nc/ras3#** 4 dq2 46 cas2# 88 dq34 130 cas6# 5 dq3 47 cas3# 89 dq35 131 cas7# 6v dd 48 we2# 90 v dd 132 r f u 7 dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n c 92 dq37 134 n c 9 dq6 51 n c 93 dq38 135 n c 10 dq7 52 n c 94 dq39 136 n c 11 dq8 53 n c 95 dq40 137 n c 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n c 103 dq46 145 n c 20 dq15 62 rfu 104 dq47 146 r f u 21 nc 63 nc 105 nc 147 nc 22 n c 64 v ss 106 n c 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n c 66 dq22 108 n c 150 dq54 25 n c 67 dq23 109 n c 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we0# 69 dq24 111 r f u 153 dq56 28 cas0# 70 dq25 112 cas4# 154 dq57 29 cas1# 71 dq26 113 cas5# 155 dq58 30 ras0# 72 dq27 114 nc/ras1#** 156 dq59 31 oe0# 73 v dd 115 r f u 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 n c 121 a9 163 n c 38 a10 80 n c 122 a11 164 n c 39 nc (a12) 81 nc 123 nc (a13) 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 r f u 167 sa2 42 r f u 84 v dd 126 r f u 168 v dd ** 256mb version only 168-pin dimm (h-14; 64mb) (h-17; 128mb) (h-30; 256mb) part numbers part number configuration speed mt8ld864ag-5 x 8 meg x 64 50ns mt8ld864ag-6 x 8 meg x 64 60ns mt16ld1664ag-5 x 16 meg x 64 50ns mt16ld1664ag-6 x 16 meg x 64 60ns mt32ld3264ag-5 x* 32 meg x 64 50ns mt32ld3264ag-6 x* 32 meg x 64 60ns *contact factory for availability note: pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. micron is a registered trademark of micron technology, inc.
2 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms toggle from valid data to high-z and back to the same valid data. if oe# is toggled or pulsed after cas# goes high while ras# remains low, data will transition to and remain high-z. during an application, if the dq outputs are wire or?d, oe# must be used to disable idle banks of drams. alternatively, pulsing we# to the idle banks during cas# high time will also tristate the outputs. inde- pendent of oe# control, the outputs will disable after t off, which is referenced from the rising edge of ras# or cas#, whichever occurs last. (refer to the 16 meg x 4 [mt4lc16m4h9] dram data sheet for additional information on edo functionality.) refresh returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. also, the chip is preconditioned for the next cycle during the ras# high time. correct memory cell data is preserved by maintaining power and ex- ecuting any ras# cycle (read, write) or ras# re- fresh cycle (ras#-only, cbr or hidden) so that all combinations of ras# addresses (a0-a10/a11) are executed at least every t ref, regardless of sequence. the cbr refresh cycle will invoke the internal refresh counter for automatic ras# addressing. serial presence-detect operation this module family incorporates serial presence- detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various dram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations be- tween the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide 8 unique dimm/eeprom addresses. general description the micron ? mt8ld864a x, mt16ld1664a x and mt32ld3264a x are randomly accessed 64mb, 128mb and 256mb memories organized in a x64 con- figuration. they are specially processed to operate from 3v to 3.6v for low-voltage memory systems. during read or write cycles, each bit is uniquely addressed through the 22/23 address bits, which are entered 12 bits (a0-a11) at ras# time and 11/12 bits (a0-a11) at cas# time. read and write cycles are selected with the we# input. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. an early write occurs when we# is taken low prior to cas# falling. a late write or read-modify-write oc- curs when we# falls after cas# was taken low. during early write cycles, the data-outputs (q) will remain high-z regardless of the state of oe#. during late write or read-modify-write cycles, oe# must be taken high to disable the data-outputs prior to applying input data. if a late write or read- modify-write is attempted while keeping oe# low, no write will occur, and the data-outputs will drive read data from the accessed location. edo page mode edo page mode is an accelerated fast-page- mode cycle. the primary advantage of edo is the availability of data-out even after cas# goes back high. edo provides for cas# precharge time ( t cp) to occur without the output data going invalid. this elimination of cas# output control provides for pipe- line reads. fast-page-mode modules have traditionally turned the output buffers off (high-z) with the rising edge of cas#. edo-page-mode drams operate like fast-page-mode drams, except data will remain valid or become valid after cas# goes high during reads, provided ras# and oe# are held low. if oe# is pulsed while ras# and cas# are low, data will 3 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms functional block diagram mt8ld864a x (64mb) dq0-dq7 dq8-dq15 dq16-dq23 dq24-dq31 dq32-dq39 dq40-dq47 dq48-dq55 dq56-dq63 a0-a11 oe2# we2# cas4# ras2# cas5# cas7# cas6# u1-u8 = mt4lc8m8c2 oe0# we0# cas0# ras0# cas1# cas3# cas2# 12 12 12 12 12 12 12 12 dq0-dq7 u1 a0 e a11 we# oe# ras# cas# dq0-dq7 u2 a0 e a11 we# oe# ras# cas# dq0-dq7 u3 a0 e a11 we# oe# ras# cas# dq0-dq7 u5 a0 e a11 we# oe# ras# cas# dq0-dq7 u6 a0 e a11 we# oe# ras# cas# dq0-dq7 u7 a0 e a11 we# oe# ras# cas# dq0-dq7 u8 a0 e a11 we# oe# ras# cas# dq0-dq7 u4 a0 e a11 we# oe# ras# cas# spd scl v dd v ss u1-u8 u1-u8 sda sa0 sa1 sa2 a0 a1 a2 4 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms functional block diagram mt16ld1664a x (128mb) dq0-dq3 dq4-dq7 dq8-dq11 dq12-dq15 dq16-dq19 dq20-dq23 dq24-dq27 dq28-dq31 dq32-dq35 dq36-dq39 dq40-dq43 dq44-dq47 dq48-dq51 dq52-dq55 dq56-dq59 dq60-dq63 u1-u16 = mt4lc16m4h9 12 12 12 12 12 12 12 12 12 12 12 12 12 12 oe0# cas1# cas2# cas3# we0# cas0# oe2# cas5# cas6# cas7# we2# cas4# a0-a11 ras0# ras2# 12 12 spd scl sda a0 a1 a2 sa0 sa1 sa2 we# oe# ras# cas# dq0-dq3 u1 a0 e a11 we# oe# ras# cas# dq0-dq3 u2 a0 e a11 we# oe# ras# cas# dq0-dq3 u3 a0 e a11 we# oe# ras# cas# dq0-dq3 u4 a0 e a11 we# oe# ras# cas# dq0-dq3 u5 a0 e a11 we# oe# ras# cas# dq0-dq3 u6 a0 e a11 we# oe# ras# cas# dq0-dq3 u7 a0 e a11 we# oe# ras# cas# dq0-dq3 u8 a0 e a11 we# oe# ras# cas# dq0-dq3 u9 a0 e a11 we# oe# ras# cas# dq0-dq3 u10 a0 e a11 we# oe# ras# cas# dq0-dq3 u11 a0 e a11 we# oe# ras# cas# dq0-dq3 u12 a0 e a11 we# oe# ras# cas# dq0-dq3 u13 a0 e a11 we# oe# ras# cas# dq0-dq3 u14 a0 e a11 we# oe# ras# cas# dq0-dq3 u15 a0 e a11 we# oe# ras# cas# dq0-dq3 u16 a0 e a11 v dd v ss u1-u16 u1-u16 5 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms functional block diagram mt32ld3264a x (256mb) u1-u32 = mt4lc16m4h9 12 12 12 12 12 12 12 12 12 12 12 12 12 12 ras1# ras3# 12 12 a0 sa0 spd scl sda a1 sa1 a2 sa2 we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 u1 u2 u3 u4 12 12 12 12 12 12 12 a0 e a11 a0 e a11 a0 e a11 a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 12 12 12 12 12 12 12 oe0# cas1# cas2# cas3# we0# cas0# oe2# cas5# cas6# cas7# we2# cas4# a0-a11 ras0# ras2# 12 12 u5 u6 u7 we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# a0 e a11 a0 e a11 a0 e a11 a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# a0 e a11 a0 e a11 a0 e a11 a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# we# oe# ras# cas# a0 e a11 a0 e a11 a0 e a11 a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 we# oe# ras# cas# a0 e a11 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u25 u26 u27 u28 u29 u30 u31 u24 u32 v dd v ss u1-u32 u1-u32 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq4-dq7 dq8-dq11 dq12-dq15 dq16-dq19 dq20-dq23 dq24-dq27 dq28-dq31 dq32-dq35 dq36-dq39 dq40-dq43 dq44-dq47 dq48-dq51 dq52-dq55 dq56-dq59 dq60-dq63 dq0-dq3 dq4-dq7 dq8-dq11 dq12-dq15 dq16-dq19 dq20-dq23 dq24-dq27 dq28-dq31 dq32-dq35 dq36-dq39 dq40-dq43 dq44-dq47 dq48-dq51 dq52-dq55 dq56-dq59 dq60-dq63 6 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms pin descriptions pin numbers symbol type description 30, 45, 114, 129 ra s0#-ras3# input row-address strobe: ras# is used to clock-in the row-address bits. two ras# inputs allow for one x64 bank or two x32 banks. 28, 29, 46, 47, 112, ca s0#-cas7# input column-address strobe: cas# is used to clock-in the 113, 130, 131 column-address bits, enable the dram output buffers and strobe the data inputs on write cycles. eight cas# inputs allow byte access control for any memory bank configuration. 27, 48 we0#, we2# input write enable: we# is the read/write control for the dq pins. we0# controls dq0-dq31. we2# controls dq32-dq63. if we# is low prior to cas# going low, the access is an early write cycle. if we# is high while cas# is low, the access is a read cycle, provided oe# is also low. if we# goes low after cas# goes low, then the cycle is a late write cycle. a late write cycle is generally used in conjunction with a read cycle to form a read-modify-write cycle. 31, 44 oe0#, oe2# input output enable: oe# is the input/output control for the dq pins. oe0# controls dq0-dq31. oe2# controls dq32-dq63. these signals may be driven, allowing late write cycles. 33-38, 117-122 a0-a11 input address inputs: these inputs are multiplexed and clocked by ras# and cas#. 2-5, 7-11, 13-17, 19-20, dq0-dq63 input/ d ata i/o: for write cycles, dq0-dq63 act as inputs 55-58, 60, 65-67, 69-72, output to the addressed dram location. byte writes may 74-77, 86-89,91-95, be performed by using the corresponding cas# 97-101, 103-104, select (x64 mode only). for read access cycles, 139-142, 144, 149-151, dq0-dq63 act as outputs for the addressed dram 153-156, 158-161 location. 42, 62, 111, 115, rfu ? reserved for future use: these pins should be left 125-126, 128, 132, 146 unc onnected. 6, 18, 26, 40, 41, 49, 59, v dd supply power supply: +3.3v 0.3v. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, v ss supply ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 82 sda input/output serial presence-detect data. sda is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 83 scl input serial clock for presence-detect. scl is used to synchronize the presence-detect data transfer to and from the module. 165-167 sa0-sa2 input presence-detect address inputs. these pins are used to configure the presence-detect device. 7 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write opera- tion have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (figures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop con- dition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver figure 1 data validity figure 2 definition of start and stop scl sda data stable data stable data change scl sda start bit stop bit 8 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms serial presence-detect matrix byte description entry (v ersion) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0 number of bytes used by micron 128 1000000080 1 total number of spd memory bytes 256 0000100008 2 memory type edo page mode 0000001002 3 number of row addresses 12 000011000c 4 number of column addresses 11 (64mb) 000010110b 12 (128mb, 256mb) 000011000c 5 number of banks 1 (64mb, 128mb) 0000000101 2 (256mb) 0000001002 6 data width x64 0100000040 7 data width (continued) none 0000000000 8 voltage interface lvttl 0000000101 9 ras# access time ( t rac) 50ns (-5) 0011001032 60ns (-6) 001111003c 10 cas# access time ( t cac) 13ns (-5) 000011010d 15ns (-6) 000011110f 11 module configuration type nonparity 0000000000 12 refresh rates 15.625 s/normal 0000000000 13 dram width (primary dram) x8 (64mb) 0000100008 x4 (128mb, 256mb) 0001000010 14 error checking dram data width none 0000000000 15-61 reserved 0000000000 62 spd revision rev. 0 0000000000 63 checksum for bytes 0-62 64mb -5 001010102a 64mb -6 0011011036 128mb -5 0011001133 128mb -6 001111113f 256mb -5 0011010034 256mb -6 0100000040 64 manufacturer ? s jedec id code mi cron 001011002c 65-71 manufacturer ? s jedec code (cont.) 11111111ff 72 manufacturing location 0000000101 0000001002 0000001103 0000010004 73-90 module part number (ascii) xxxxxxxxxx 91 pcb identification code 1 0000000101 2 0000001002 3 0000001103 4 0000010004 92 identification code (cont.) 0 0000000000 93 year of manufacture in bcd xxxxxxxxxx 94 week of manufacture in bcd xxxxxxxxxx 95-98 module serial number xxxxxxxxxx 99-125 manufacture specific data (rsvd) ????????? note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data. 9 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms absolute maximum ratings* voltage on v dd pin relative to v ss ........ -1v to +4.6v voltage on inputs or i/o pins relative to v ss ................................. -1v to +4.6v operating temperature, t a (ambient) .. 0c to +70c storage temperature (plastic) ........... -55c to +125c power dissipation ................................................... 8w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol size min max units notes supply voltage v dd all 3 3.6 v input high voltage: logic 1; all inputs v ih all 2 v dd + 0.3 v 30 input low voltage: logic 0; all inputs v il all -0.5 0.8 v 30 input leakage current 64mb -2 2 any input 0v v in v dd + 0.3v cas0#-cas7# i i 1 128mb -4 4 a (all other pins not under test = 0v) 256mb -8 8 64mb -16 16 a0-a11 i i 2 128mb -32 32 a 256mb -64 64 64mb -8 8 we0#, we2#, i i 3 128mb -16 16 a oe0#, oe2# 256mb -32 32 64mb -8 8 ras0#-ras3# i i 4 128mb -16 16 a 256mb -16 16 output leakage current: 64mb -5 5 dq is disabled; 0v v out v dd + 0.3v dq0-dq63 i oz 128mb -5 5 a 256mb -10 10 output levels: v oh all 2.4 ? v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol all ? 0.4 v 10 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms i cc operating conditions and maximum limits (notes: 1, 5, 6) (v dd = +3.3v 0.3v) parameter/condition symbol size -5 -6 units notes standby current: ttl 64mb 8 8 (ras# = cas# = v ih )i cc 1 128mb 16 16 ma 256mb 32 32 standby current: cmos 64mb 4 4 (ras# = cas# = v dd - 0.2v) i cc 2 128mb 8 8 ma 256mb 16 16 operating current: random read/write 64mb 1,400 1,320 average power supply current i cc 3 128mb 2,720 2,560 ma 3, 24 (ras#, cas#, address cycling: t rc = t rc [min]) 256mb 2,736 2,576 operating current: edo page mode 64mb 1,240 1,000 average power supply current i cc 4 128mb 2,400 1,920 ma 3, 24 (ras# = v il , cas#, address cycling: t pc = t pc [min]) 256mb 2,416 1,936 refresh current: ras#-only 64mb 1,400 1,320 average power supply current i cc 5 128mb 2,720 2,560 ma 3, 24 (ras# cycling, cas# = v ih : t rc = t rc [min]) 256mb 2,736 2,576 refresh current: cbr 64mb 1,320 1,240 average power supply current i cc 6 128mb 2,560 2,400 ma 3, 4 (ras#, cas#, address cycling: t rc = t rc [min]) 256mb 2,576 2,416 max capacitance parameter symbol 64mb 128mb 256mb units notes input capacitance: a0-a11 c i 1 46 86 168 p f 2 input capacitance: we0#, we2#, oe0#, oe2# c i 2 32 60 118 p f 2 input capacitance: ras0#-ras3# c i 3 32 60 60 p f 2 input capacitance: cas0#-cas7# c i 4 10 18 32 p f 2 input capacitance: scl, sa0-sa2 c i 5 666pf2 input/output capacitance: dq0-dq63, sda c io 12 12 22 p f 2 max 11 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 29) (v dd = +3.3v 0.3v) ac characteristics -5 -6 parameter symbol min max min max units notes access time from column address t aa 25 30 ns column-address setup to cas# t ach 12 15 ns precharge during writes column-address hold time (referenced to ras#) t ar 38 45 ns column-address setup time t asc 0 0 ns row-address setup time t asr 0 0 ns column address to we# delay time t awd 42 49 ns 23 access time from cas# t cac 13 15 ns 14 column-address hold time t cah 8 10 ns cas# pulse width t cas 8 10,000 10 10,000 ns cas# hold time (cbr refresh) t chr 8 10 ns 4 cas# to output in low-z t clz 0 0 ns data output hold after cas# low t coh 3 3 ns cas# precharge time t cp 8 10 ns 15 access time from cas# precharge t cpa 28 35 ns cas# to ras# precharge time t crp 5 5 ns cas# hold time t csh 38 45 ns cas# setup time (cbr refresh) t csr 5 5 ns 4 cas# to we# delay time t cwd 30 35 ns 23 write command to cas# lead time t cwl 8 10 ns data-in hold time t dh 8 10 ns 22 data-in setup time t ds 0 0 ns 22 output disable t od 0 12 0 15 ns output enable t oe 12 15 ns oe# hold time from we# during t oeh 8 10 ns read-modify-write cycle oe# high hold time from cas# high t oehc 5 10 ns oe# high pulse width t oep 5 5 ns oe# low to cas# high setup time t oes 4 5 ns output buffer turn-off delay t off 0 12 0 15 ns 19, 27 oe# setup prior to ras# t ord 0 0 ns 19 during hidden refresh cycle edo-page-mode read or write cycle time t pc 20 25 ns edo-page-mode read-write cycle time t prwc 47 56 ns access time from ras# t rac 50 60 ns 13 ras# to column-address delay time t rad 9 12 ns 17 row-address hold time t rah 9 10 ns ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 50 125,000 60 125,000 ns random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 11 14 ns 16 read command hold time (referenced to cas#) t rch 0 0 ns 18 read command setup time t rcs 0 0 ns 12 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 29) (v dd = +3.3v 0.3v) ac characteristics -5 -6 parameter symbol min max min max units notes refresh period (4,096 cycles) t ref 64 64 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns read command hold time (referenced to ras#) t rrh 0 0 ns 18 ras# hold time t rsh 13 15 ns read-write cycle time t rwc 116 140 ns ras# to we# delay time t rwd 67 79 ns 23 write command to ras# lead time t rwl 13 15 ns transition time (rise or fall) t t250250ns write command hold time t wch 8 10 ns write command hold time (referenced to ras#) t wcr 38 45 ns we# command setup time t wcs 0 0 ns output disable delay from we# (cas# high) t whz 12 15 ns write command pulse width t wp 5 5 ns we# pulse width for output t wpz 10 10 ns disable when cas# high we# hold time (cbr refresh) t wrh 8 10 ns we# setup time (cbr refresh) t wrp 8 10 ns 13 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms serial presence-detect eeprom operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i cc ? 2ma scl clock frequency = 100 khz serial presence-detect eeprom ac electrical characteristics (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wr 10 ms 28 14 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms 19. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 20.a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 21.the maximum current ratings are based with the memory operating or being refreshed in the x64 mode. the stated maximums may be reduced by approximately one-half when used in the x32 mode. 22.these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 23. t wcs, t rwd, t awd and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. if t wcs > t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. t rwd, t awd and t cwd define read- modify-write cycles. meeting these limits allows for reading and disabling output data and then applying input data. oe# held high and we# taken low after cas# goes low result in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 24.column address changed once each cycle. 25.the 3ns minimum parameter guaranteed by design. 26.measured with the specified current load and 100pf. 27. t off on an edo module is determined by the latter of the ras# and cas# signals to transition high. 28.the spd eeprom write cycle time ( t wr) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/ program cycle. during the write cycle, the eeprom bus interface circuit are disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. 29.if oe# is tied permanently low, late write or read-modify-write operations are not possible. 30. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#-only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 2ns for -5 and 2.5ns for -6. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 10.if cas# and ras# = v ih , data output is high-z. 11.if cas# = v il , data output may contain data from the last valid read cycle. 12.measured with a load equivalent to two ttl gates and 100pf and v ol = 0.8v and v oh = 2v. 13.requires that t aa and t cac are not violated. 14.requires that t aa and t rac are not violated. 15.if cas# is low at the falling edge of ras#, output data will be maintained from the previous cycle. to initiate a new cycle and clear the data- out buffer, cas# must be pulsed high for t cp. 16.the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd (max) limit, t aa and t cac must always be met. 17.the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac and t cac must always be met. 18.either t rch or t rrh must be satisfied for a read cycle. 15 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column cas# we# note 1 t ach don ? t care undefined note: 1. t off is referenced from rising edge of ras# or cas#, whichever occurs last. t off 0 12 0 15 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh1315ns -5 -6 symbol min max min max units timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns t oe 12 15 n s 16 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms early write cycle don ? t care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh we# cas# t ach -5 -6 symbol min max min max units t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rp 30 40 n s t rsh1315ns t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns t rad 9 12 ns 17 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo-page-mode read cycle valid data valid data valid data column column column row row don ? t care undefined t od t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# t cas t cas cas# we# t coh t oep t oehc t oes t oes t ach t ach t ach -5 -6 symbol min max min max units t oehc 5 10 ns t oep 5 5 ns t oes 4 5 ns t off 0 12 0 15 ns t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rrh 0 0 ns t rsh1315ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t od 0 12 0 15 ns t oe 12 15 n s 18 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ach t ach t ach t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# oe# v v ih il don ? t care undefined -5 -6 symbol min max min max units t pc 20 25 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rp 30 40 n s t rsh1315ns t rwl 13 15 n s t wch 8 10 ns t w c r 38 45 n s t wcs 0 0 ns t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t cah 8 10 ns t cas 8 10,000 10 10,000 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns 19 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms read-write cycle (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach cas# don ? t care undefined -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t rwc 116 140 ns t rwd6779ns t rwl 13 15 n s t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t crp 5 5 ns t c s h 38 45 n s t cwd3035ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns 20 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo-page-mode read-write cycle (late write and read-modify-write cycles) don ? t care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t cas t rsh t cp t rp t rasp t cas t cp t cas t rcd t csh t pc t crp row column column column row v v ih il cas# v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# we# t prwc t oeh t od t od t od note 1 note: 1. t pc is for late write cycles only. -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t oeh 8 10 ns t pc 20 25 n s t prwc 47 56 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t rwd6779ns t rwl 13 15 n s t wp 5 5 ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t a w d 42 49 n s t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t cwd3035ns t cwl 8 10 ns t dh 8 10 ns t ds 0 0 ns 21 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo-page-mode read early write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas# t cas t cas t cp t cp don ? t care undefined -5 -6 symbol min max min max units t oe 12 15 n s t pc 20 25 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t rasp 50 125,000 60 125,000 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t rp 30 40 n s t rsh1315ns t wch 8 10 ns t wcs 0 0 ns t whz 12 15 n s timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t a c h 12 15 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t coh 3 3 ns t cp 8 10 ns t cpa 28 35 n s t crp 5 5 ns t c s h 38 45 n s t dh 8 10 ns t ds 0 0 ns 22 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms edo read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz don ? t care undefined cas# -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t r c d 11 14 n s t rch 0 0 ns t rcs 0 0 ns t whz 12 15 n s t wpz 10 10 n s timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t cas 8 10,000 10 10,000 ns t clz 0 0 ns t cp 8 10 ns t crp 5 5 ns t c s h 38 45 n s 23 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms ras#-only refresh cycle row v v ih il cas# v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc we# v v ih il cbr refresh cycle (addresses, oe# = don ? t care) t rp v v ih il ras# t ras open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# don ? t care undefined note 1 -5 -6 symbol min max min max units t ras 50 10,000 60 10,000 ns t rc 84 104 ns t rp 30 40 n s t rpc 5 5 ns t wrh 8 10 ns t wrp 8 10 ns timing parameters -5 -6 symbol min max min max units t asr 0 0 ns t chr 8 10 ns t cp 8 10 ns t crp 5 5 ns t csr 5 5 ns t rah 9 10 ns 24 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms hidden refresh cycle 20 (we# = high; oe# = low) don ? t care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rc t rp t chr t ras dq v v ioh iol v v ih il addr v v ih il cas# v v ih il ras# -5 -6 symbol min max min max units t off 0 12 0 15 ns t ord 0 0 ns t r a c 50 60 n s t rad 9 12 ns t rah 9 10 ns t ras 50 10,000 60 10,000 ns t rc 84 104 ns t r c d 11 14 n s t rp 30 40 n s t rsh1315ns timing parameters -5 -6 symbol min max min max units t a a 25 30 n s t ar 38 45 n s t asc 0 0 ns t asr 0 0 ns t c a c 13 15 n s t cah 8 10 ns t chr 8 10 ns t clz 0 0 ns t crp 5 5 ns t od 0 12 0 15 ns t oe 12 15 n s 25 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms spd eeprom scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s symbol min max units 26 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms 168-pin dimm df-16 (64mb) .200 (5.08) max .054 (1.37) .046 (1.17) 1.105 (28.07) 1.095 (27.81) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) 168-pin dimm df-27 (128mb) .350 (8.89) max .054 (1.37) .046 (1.17) 1.255 (31.88) 1.245 (31.62) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) note: all dimensions in inches (millimeters) max or typical where noted. min 27 8, 16, 32 meg x 64 nonbuffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm78.p65 ? rev. 2/99 ?1999, micron technology, inc. 8, 16, 32 meg x 64 nonbuffered dram dimms 168-pin dimm df-41 (256mb) .350 (8.89) max .054 (1.37) .046 (1.17) 2.005 (51.93) 1.995 (50.67) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc. note: all dimensions in inches (millimeters) max or typical where noted. min |
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